1. Field of the Invention
The present invention relates to a test circuit for a system logic, and more specifically to a test circuit for executing a test by changing over between an existing macro and a newly created circuit. Furthermore, the present invention relates to a test method performed by using the test circuit.
2. Description of Related Art
A boundary scan design based on the IEEE 1149.1 standard is one test facilitating design procedure for facilitating a test of a system circuit designed on a circuit board. In this boundary scan design, an LSI chip on a board is regarded as an internal logic in an overall system, and scannable flipflop are added to all input/output pins of the LSI as control points and observing points, in order to make it possible to write a test data to the internal LSI from an external of the board (control) and to read out an internal data from the internal LSI to an external of the board (observation).
Referring to FIG. 1, there is shown a diagram for illustrating a prior art boundary scan circuit. A number of boundary scan cells (BS) 10, each of which is a one-bit shift register, are located between a system logic 12 and terminals 8 of a circuit board 6. The boundary scan cells (BS) 10 are connected in series to constitute a boundary scan cell chain. A test data inputted from a TDI terminal (this terminal and other terminals are representatively designated with Reference Numeral 14) is supplied to a test access port (TAP) 16, and then further supplied from a boundary scan-in terminal BSin into the boundary scan cell chain. An output of a system logic 12 is supplied from a boundary scan-out terminal BSout to the test access port 16, and further, outputted from a data output terminal TDO 18 and compared with an expected data by an LSI tester. This boundary test is executed by supplying a boundary scan test control signal BStest generated in the test access port 16, to a selector 11 of each boundary scan cell 10.
In the system circuit designing, it is an ordinary practice that a portion of the circuit is constituted by utilizing an existing circuit or chip whose design has been already completed, without newly creating the whole of the circuit. In this specification, this existing circuit or chip will be called a xe2x80x9cmacroxe2x80x9d.
In the case that both the macro and a newly created circuit chip are mounted on a single circuit board, the prior art boundary scan circuit shown in FIG. 1 cannot carry out the test by changing over between the macro and the newly created circuit chip, since no function is provided for testing only the macro independently.
Accordingly, it is an object of the present invention to provide a test circuit for executing a test by changing over between an existing macro and a newly created circuit.
Another object of the present invention is to provide a test method for executing a test by changing over between an existing macro and a newly created circuit.
The above and other objects of the present invention are achieved in accordance with the present invention by a test circuit for testing a system logic composed of an existing macro and a newly created circuit which are mounted on a circuit board, the test circuit including a boundary scan circuit for testing the newly created circuit, and a macro test circuit for testing only the existing macro independently. The macro test circuit and the boundary scan circuit are unified so that by controlling one or two selectors, the macro test circuit and the boundary scan circuit are caused to function independently of each other.
If the test is carried out by using this test circuit, the test for the newly created circuit and the test for the existing macro can be carried out by changing over one to another. Thus, the test for the newly created circuit is carried out by using the boundary scan circuit, and the test for the existing macro is carried out by the macro test circuit.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.